1. Field of the Invention
This invention relates in general to the fabrication of integrated circuit (IC) devices, and more particularly to a method of fabricating a high-voltage metal-gate CMOS device having heavily doped source and drain regions that are precisely formed within the lightly doped source and drain regions, so as to guarantee the uniformity of device characteristics.
2. Description of the Prior Art
Under current technology of fabricating high-voltage CMOS devices, a polysilicon layer is normally used as the gate electrode of a CMOS device. The polysilicon gate electrode configuration, however, requires a relatively long manufacturing cycle time. Thus the manufacturing cost is raised by such a long cycle time. Furthermore, due to their inherent characteristics, CMOS devices with polysilicon gate electrodes usually encounter a latch-up problem which is fatal to the operation of the devices.
By replacing the polysilicon gate electrode with a metal gate electrode, the cycle time of manufacturing a high-voltage CMOS device can be reduced and the latch-up problem can be prevented. However, the conventional process for fabricating a high-voltage metal-gate CMOS device suffers from poor dimensional alignment and symmetry for the fabricated source/drain regions that are prerequisites for the uniformity of the electrical characteristics for these CMOS devices fabricated. These poor alignment and symmetry characteristics found in the conventional fabrication processes are inherent to the nature of the fabrication process steps employed. Poor alignment in the source and drain regions of the CMOS device result in variations of the electrical characteristics for CMOS devices produced in different production batches, as the fabrication process conditions may vary for the alignments involved in the process steps.